The present disclosure relates to non-volatile memory structures, and more particularly, to techniques for forming electrical contacts between bit lines and storage elements in such structures.
Semiconductor memory has become increasingly popular for use in various electronic devices. For example, non-volatile semiconductor memory is used in cellular telephones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices and other devices. Electrically Erasable Programmable Read Only Memory (EEPROM) and flash memory are among the most popular non-volatile semiconductor memories. With flash memory, also a type of EEPROM, the contents of the whole memory array, or of a portion of the memory, can be erased in one step, in contrast to the traditional, full-featured EEPROM.
One type of flash memory is commonly referred to as NAND memory, which includes multiple floating gate transistors (memory cells) in series between two select gate transistors. One of the select gates connects the NAND string to a bit line through a bit line contact. Note that there may be many NAND strings that share the same bit line. For example, in some designs, a single bit line is associated with many NAND strings that run in a long line. The select gate transistors are used to select one of the NAND strings on the bit line. In some devices, a bit line contact connects the bit line to a diffusion region that is between two select gate transistors—one for each of two different NAND strings.
Typically, the memory array is arranged with a large number of parallel bit lines, along with parallel word lines that run perpendicular to the bit lines. By applying suitable voltages to the bit line and word lines the memory cells may be programmed. The memory cells may be read by applying appropriate voltages to the word lines and bit lines, and then sensing the bit lines.
As sizes of memory arrays continue to shrink, the width and pitch of bit lines continues to shrink. As a result it can be difficult to properly fabricate bit line contacts within the tight design constraints. For example, the lithographic process may have limitations on how closely the bit line contacts can be placed to one another. Therefore, if the design calls for too narrow of a pitch for the bit line contact, they may not print properly. Also, it is possible for bit line contacts to short together electrically.
However, even with state-of-the-art lithography, it can be difficult to fabricate bit line contacts. For example, some lithography techniques may be more suitable for forming dense line/spaces than for hole/pillars. For example, spacer techniques may be used to form dense line/spaces beyond the single resolution limit. Forming dense line/spaces may be suitable for forming the bit lines themselves. However, formation of the bit line contacts may require more of a hole/pillar approach. Therefore, other techniques may be needed for forming the bit line contacts.
One technique for alleviating such problems is to stagger the placement of the bit line contacts. For example, a first row of bit line contacts may be formed for odd bit lines and a second row for even bit line contacts. The two rows run parallel to one another, but have a small gap between them. The small space between the rows creates a staggering which helps to alleviate design constraints. In other words, bit line contacts for the odd bit lines are staggered from bit line contacts for the even bit lines. However, even staggering the bit line contacts may not be sufficient, especially as the size of features continues to shrink.
Therefore, improved techniques are desired for forming bit line contacts in memory arrays.